1. Field of the Invention
The present invention relates to a test system and a test method of a semiconductor integrated circuit.
2. Description of Related Art
In large-scale-integrations (LSIs) used in various systems, internal operation and input/output are becoming faster with increasing sophistication and higher levels of integration. There is thus a demand for a high-speed tester compatible with the increasing LSI operating speed. However, a low-cost test method using a hitherto used tester is desired in terms of cost reduction.
As a low-cost test method of a high-speed I/O made up of a high-speed input device and a high-speed output device, a loop-back test is used that connects an external input terminal of the high-speed input device and an external output terminal of the high-speed output device through a transmission line.
FIG. 11 shows a schematic view of a test system 1 for a loop-back test of a semiconductor integrated circuit including high-speed input/output devices disclosed in Japanese Unexamined Patent Application Publication No. 2003-167034. The test system 1 sets a measurement target semiconductor integrated circuit LSI1 on a test board 2 and performs measurement. The semiconductor integrated circuit LSI1 includes high-speed input devices RX1 to RX4, high-speed output devices TX1 to TX4, test pattern generation devices TPG1 to TPG4 and test pattern check devices TPC1 to TPC4.
The test board 2 is provided with loop-back paths LPB1 to LPB4, and external output terminals of the high-speed output devices TX1 to TX4 and external input terminals of the high-speed input devices RX1 to RX4 are connected through the loop-back paths LPB1 to LPB4, respectively.
An operation of the test system 1 is described briefly. Output signals corresponding to test patterns generated by the test pattern generation devices TPG1 to TPG4 are output to the loop-back paths LPB1 to LPB4 from the high-speed output devices TX1 to TX4. The output signals are then input to the high-speed input devices RX1 to RX4 through the loop-back paths LPB1 to LPB4. After that, the test pattern check devices TPC1 to TPC4 check the occurrence of an error or the like on the signals input to the high-speed input devices RX1 to RX4.
In this manner, by using the loop-back paths LPB1 to LPB4, a self-test can be performed inside the semiconductor integrated circuit LSI1 with use of the test pattern generation devices TPG1 to TPG4, the test pattern check devices TPC1 to TPC4, the high-speed output devices TX1 to TX4 and the high-speed input devices RX1 to RX4 incorporated in the semiconductor integrated circuit LSI1. It is thereby possible to conduct a characteristics test of the high-speed I/O without need to prepare a high-speed tester including high-speed input/output devices, thus enabling reduction of the test cost.